This invention relates generally to semiconductor processing, and more particularly to a method and process for dual inlaid structures for integrated circuit interconnections.
Integrated circuits (ICs) are formed on semiconductor substrates using a number of different processing steps to create transistor and interconnection elements. In order to electrically connect transistor terminals associated with the semiconductor substrate, conductive (e.g., metal) vias (vertical channels) and interconnections (interconnects) are formed in dielectric (electrically insulating) materials as part of the integrated circuit. The vias and interconnects couple electrical signals and power between transistors, internal circuits of the IC, and circuits external to the IC.
Dual inlaid (xe2x80x9cdamascenexe2x80x9d) interconnect processes for semiconductor devices are replacing conventional blanket metal deposition and etch processes. Traditionally, metal films have been deposited and patterned using photolithography techniques to form patterned metal interconnects overlying a semiconductor substrate. As interconnect geometry sizes decrease and as conductive lines are formed closer together, it becomes increasingly difficult to accurately pattern the conductive lines and form the conductive interconnects using the traditional blanket deposition and patterning processes. Consequently, inlaid metal interconnect processes have been developed to overcome some of these problems.
An example of a conventional self-aligned dual damascene process is depicted in prior art FIGS. 1A-1E. FIG. 1A shows an etch stop layer (xe2x80x9cESLxe2x80x9d) 13, such as silicon nitride, that is deposited over an existing interconnect pattern formed in an interconnect layer 10. The interconnect layer 10 may include a patterned conductive material 12, such as copper. A layer of low-k dielectric material 16 is then deposited on the bottom ESL 13. A middle stop layer (xe2x80x9cMSLxe2x80x9d) 18, such as silicon dioxide or SiN, is deposited over the low-k dielectric material 16. A via pattern 19 is then etched into the MSL 18 using conventional photolithography and etching techniques, as illustrated in FIG. 1A.
A second layer of low-k dielectric material 22 is deposited or spin-coated on the MSL 18 and the opening 19 formed in the MSL 18. A cap, or hard mask layer 24, such as silicon dioxide or SiON, is then deposited on the dielectric layer 22, as illustrated in prior art FIG. 1B.
A trench and via pattern is then formed using conventional photolithography techniques, for example, with a photoresist and an anisotropic dry etch. A first anisotropic dry etch etches through cap layer 24, followed by a second anisotropic dry etch 25 that etches through dielectric layers 22 and 16 but not the cap layer 24, MSL 18 or ESL 13. The second etch 25 results in the formation of a trench 26 and a via 28, as illustrated in prior art FIG. 1C.
In prior art FIG. 1D the exposed portion of the ESL 13 is then removed by a different etch, etch 27, to expose the conductor 12 so that the conductor may connect to overlying conductive lines through the trench 26 through the via 28, respectively.
Following formation of the trenches and vias, a conductive material 30 may be deposited through any of numerous conventional means into the opening and polished back by CMP to level 32. Cap layer 24 serves as a stop layer during CMP, as illustrated in prior art FIG. 1E.
Removing the ESL layer 13 from the trenches 26 and the vias 28 prior to filling them with conductive material creates several deleterious effects. In particular, when the ESL layer 13 is etched from the via 28, the cap layer 24 and the MSL 18 are also etched to some degree, causing the corners of the cap layer and MSL to become rounded near the trenches 26 and vias 28. The cap 24 and the MSL 18 must therefore be thick enough to survive the ESL etch and protect the underlying ILD layers 16 and 22. Utilizing thick cap and middle layers, however, comes at the expense of the dielectric constant of the xe2x80x9cstackxe2x80x9d (i.e., the layers of the ESL, ILDs, MSL, and cap). Because the thickness of the cap 24 and the MSL 18 depend, in part, on surviving the ESL etch, the layers are not necessarily optimized to have the lowest dielectric stack constant. Further, non-uniform ESL etching from feature loading effects may lead to poorly defined trench heights.
In addition, corner rounding induced during the via definition of the MSL 18, as illustrated in FIG. 1A, may further complicate the final profile and require additional thickness increases in the MSL 18 to insure that the corners can survive the subsequent etches. Increased thickness of the MSL 18, however, undesirably leads to a higher dielectric constant of the stack.
An additional complication that needs to be considered is the transition from relatively thick 248 nm photoresists to thinned 248 nm photoresists, 193 nm photoresists, and even bi-layer or tri-layer photoresists. Each of these changes can lead to complications since robustness to the etch process is significantly different in each of these scenarios.
Additionally, after the trenches 26 and vias 28 are filled with the conductive material 30, a top surface 32 thereof must be polished back to the hard cap layer 24 in order to remove the metal from the surface and isolate the interconnect patterns. The corner rounding of the cap layer 24 may require additional polishing of the conductive layer 30 to isolate the interconnect patterns, and such additional polishing may damage the underlying ILD layer 22. As interconnect patterns become more dense, corner rounding of the cap layer 24 leads to increasingly thick cap layers or dual layers to compensate for the additional polishing needed to isolate the interconnect features.
Further, the ESL etch can cause ILD attack and modification due to the etchant contacting the sidewalls of the ILD trenches 26 and vias 28. This attack on the ILD layer sidewalls may lead to a higher dielectric constant of the stack and decreased performance of the interconnect patterns. Also, under-layer sputtering of copper (when copper is employed as the underlying conductive structure 12) on the ILD layer sidewalls may increase electromigration and leakage of copper within the structure.
A further problem of conventional dual inlaid metal interconnect processing is feature dependent loading effects during the etch process. Further, certain areas, such as near the die seal or lithography alignment marks, can etch significantly faster than other areas of the die. This difference in etch rate can lead to punch through of the ESL 13 in the fast etching areas. Further, these fast etching areas can have charge build-up which can result in conductor charging and explosion.
Therefore, a method and process for dual inlaid processing is desired that allows for optimal thickness of the cap and MSL materials to improve the dielectric constant of the stack, requiring less polishing to isolate features (e.g. less corner rounding), and allows for the use of single layer photoresists. It is also desired to provide a method that minimizes ILD attack and modification, and prevents underlying sputtering on the ILD sidewalls to improve the dielectric constant and electromigration performance of the stack. Further, it is desired to optimize the ESL for electromigration performance, decreased dielectric constant, and prevent possible punch through of the ESL layer during the ESL etch.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
According to one aspect of the present invention, a method is provided for forming a dual inlaid structure for an IC interconnect. The method includes forming an etch stop layer over an integrated circuit substrate structure, forming an opening in a portion of the etch stop layer, and forming a first ILD, a MSL, a second ILD and two cap layers over the etch stop layer and the opening formed therein. The method further includes forming a photoresist pattern over the cap layers, and etching the top cap layer to form an opening therein that will correspond to a trench. Another photoresist is then formed, patterned and employed as a mask to pattern the bottom cap layer to form an opening therein that will correspond to a via. The bottom cap layer is then employed to form a via down to the substrate through the second ILD. The top cap layer is then employed to pattern the bottom cap and second ILD to form a trench which stops on the MSL. Simultaneously or concurrently to opening the bottom cap, a portion of the MSL is etched, opening and defining the via therein. The via ILD is then etched simultaneously or concurrently with the trench ILD to define the via opening. This method is known as the trench first dual hard mask approach. According to another aspect of the present invention, the methodology includes forming openings in the dielectric and cap materials that are aligned substantially with the etch stop layer opening, and filling the opening with a conductive material, for example, metal.
The method for forming the inlaid structure may further include forming a barrier layer within the opening of the etch stop layer prior to forming the layer of dielectric material over the etch stop layer, and removing a portion of the barrier layer that does not fill the exposed etch stop layer opening. The barrier layer comprises, for example, tantalum, and the dielectric material comprises SiLK or another material with a dielectric constant of approximately 3.0 or less, for example. The cap layer has a thickness of, for example, less than about 2000 A. The photoresist mask used to etch the cap layer and the interlevel dielectric (ILD) layer is, in one example, a single layer, and the pattern of the photoresist is, in one example, aligned with openings of the etch stop layer. The conductive material filling the via or trench comprises, for example, copper.
According to another aspect of the present invention, a method is provided for forming an integrated circuit interconnect structure. The method includes forming a first etch stop layer on an integrated circuit structure, forming a second etch stop layer (ESL) on the first etch stop layer, patterning the second ESL so that it remains in the areas on the die that, due to the feature dependent loading effect, for example, etch quickly. A layer of dielectric material is then formed over the first ESL and the second patterned ESL. A MSL, another layer of dielectric material and a cap layer are formed over the first layer of dielectric material. A photoresist mask is then formed over the cap layer, and the cap, second layer of dielectric material, MSL and first layer of dielectric material are etched, stopping on or in the second patterned ESL layer in the fast etching areas and in the first ESL layer in the slower etching areas. A trench photoresist mask is then utilized to further pattern the trench dielectric level with final removal of the ESLs. The dual damascene pattern is then filled with a conductive material, such as copper.
The method may further include etching the first and second etch stop layers from the pattern where the first and second etch stop layers may be the same or different materials. The first etch stop layer may have a lower dielectric constant than the second etch stop layer, and the thickness of the first etch stop layer may further be based upon the electromigration performance of the first etch stop layer material.
All examples of the present invention highlighted herein are applicable to both via and trench damascene patterning, and both such processes are contemplated as falling within the scope of the present invention.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.